1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device requiring a high breakdown voltage.
2. Description of the Background Art
It is important that a semiconductor device constituted to block a high voltage by a pn junction is to relieve an electric field strength of a junction surface provided in contact with a substance having a different dielectric constant and is to stably implement a breakdown voltage as designed as compared with a junction electric field strength in a silicon substrate.
For this reason, a field limiting ring structure, an SIPOS (Semi-Insulating Polycrystalline Silicon) structure and the like have generally been used as a junction termination processing structure.
 less than SIPOS Structure greater than 
FIG. 13 shows a sectional structure of a silicon diode 80 having an SIPOS structure as a junction termination processing structure.
As shown in FIG. 13, the silicon diode 80 comprises a p-type impurity layer 202 provided as an operation region of the diode and containing a p-type impurity in a relatively high concentration (p+), and a p-type impurity layer 208 having a part thereof overlapping with an edge portion of the p-type impurity layer 202 and containing the p-type impurity extended in a horizontal direction toward an outer peripheral portion in a relatively low concentration (pxe2x88x92) in one of main surfaces of a silicon substrate 201 containing an n-type impurity in a relatively low concentration (nxe2x88x92).
The p-type impurity layer 208 has a 3-step shape. The steps overlap each other and have the whole shape such that a junction depth and a concentration are reduced toward the outer periphery. The p-type impurity layer 208 is provided to surround the p-type impurity layer 202 on a plane.
A maximum depth of the p-type impurity layer 208 is 20 xcexcm in a device having a breakdown voltage of 1.2 kV and 70 xcexcm in a device having a breakdown voltage of 5 kV, for example. Moreover, the p-type impurity layer 202 has a depth of 5 to 40 xcexcm.
An anode electrode 204 is provided on the p-type impurity layer 202 and an SIPOS film 206 is provided from an upper part of the p-type impurity layer 208 to an upper part of the outer peripheral portion, and a silicon nitride film (Si3N4) 207 is provided on the SIPOS film 206.
The SIPOS film 206 has a thickness of 500 xcexcm and contains 10% of oxygen, for example. Moreover, the silicon nitride film 207 has a thickness of 150 nm.
An n-type impurity layer 203 containing an n-type impurity in a relatively high concentration (n+) is provided in the other main surface of the silicon substrate 201 and a cathode electrode 205 is provided on the n-type impurity layer 203.
Thus, the p-type impurity layer 208 having the 3-step shape is provided to surround the operation region of the diode. Therefore, a depletion layer DL is extended during the operation of the device so that an electric field of a pn junction portion can be relieved and a breakdown voltage can be maintained.
In the case in which a backward voltage is applied to the silicon diode 80, a current flows to the SIPOS film 206 so that the SIPOS film 206 can stabilize an electric field distribution of the semiconductor substrate 201.
Moreover, the silicon nitride film 207 functions as a protective film, thereby contributing to stable maintenance of the breakdown voltage.
Next, a method of forming the p-type impurity layer 208 will be described with reference to FIG. 14. As shown in FIG. 14, the p-type impurity layer 202 is formed in one of the main surfaces of the silicon substrate 201 and a resist mask RM is then subjected to patterning on the main surface of the silicon substrate 201.
The resist mask RM has such a pattern that an opening OP1 having a large area corresponding to an area of the deepest diffusion layer is provided on the same diffusion layer in the p-type impurity layer 208 having three steps, and a plurality of openings OP2 are provided on two other diffusion layers and the number of the openings OP2 is decreased when a diffusion depth is reduced.
By using the resist mask RM having such a structure for an ion implantation mask, an effective implantation amount can be changed for each diffusion layer and the p-type impurity layer 208 having the 3-step shape can be obtained by thermal diffusion after ion implantation.
 less than Field Limiting Ring Structure greater than 
Next, a sectional structure of a silicon carbide diode 90 having a field limiting ring structure as a junction termination processing structure will be described with reference to FIG. 15.
Since silicon carbide has a greater energy gap between bands than that of silicon, it has a great thermal stability so that a silicon carbide device can be operated at a high temperature of 1000 K (Kelvin) or less. In addition, the silicon carbide has a high thermal conductivity. Therefore, the silicon carbide device can be provided at a high density.
Moreover, the silicon carbide has a breakdown electric field which is approximately ten times as great as that of silicon. In a conduction blocking state, therefore, the silicon carbide is suitable for a device to be operated on a condition that a high voltage might be generated.
On the other hand, the SIPOS structure has a great temperature dependency. In the silicon carbide diode having a large operating temperature range, therefore, there is a possibility that a voltage blocking capability might be extremely changed at low and high temperatures. Consequently, it is not desirable that the SIPOS structure should be applied to the silicon carbide diode. For this reason, the field limiting ring structure is generally applied to the silicon carbide diode.
As shown in FIG. 15, in the silicon carbide diode 90, an n-type epitaxial layer 303 containing an n-type impurity in a relatively low concentration (nxe2x88x92) is provided on one of main surfaces of a silicon carbide substrate 301 containing the n-type impurity in a relatively high concentration (n+).
The n-type epitaxial layer 303 takes a step shape having a protrusion PP and a base bottom portion BP, and a p-type impurity layer 302 containing a p-type impurity in a relatively high concentration (p+) and acting as an operation region of the diode is provided in a surface of the protrusion PP.
A side surface of the protrusion PP is constituted such that a side surface of the n-type epitaxial layer 303 has an inclination with respect to a pn junction interface of the n-type epitaxial layer 303 and the p-type impurity layer 302. Thus, a bevel structure is obtained.
A silicon oxide film 307 is provided from the side surface of the protrusion PP from which a junction end of the pn junction is exposed to a surface of the base bottom portion BP, and the junction end is not directly exposed.
Moreover, the base bottom portion BP is selectively provided with a p-type impurity layer 308 containing a p-type impurity in a relatively low concentration (pxe2x88x92) to surround the protrusion PP, thereby constituting a field limiting ring. The field limiting ring is set in a floating state.
An anode electrode 304 is provided on the p-type impurity layer 302 and a cathode electrode 305 is provided on the other main surface of the silicon carbide substrate 301.
Since the field limiting ring 308 is thus provided to surround the operation region of the diode, a high breakdown voltage can be implemented. More specifically, when a backward bias is applied to the diode 90, a depletion layer is first formed around a main junction. When the backward bias is increased, the depletion layer is extended toward the outer peripheral side and the main junction and the field limiting ring punch through before avalanche breakdown of the main junction is caused. Consequently, a maximum field effect of a curved portion of the main junction can be relieved and a breakdown voltage can be maintained.
A method of manufacturing the silicon carbide diode 90 will be described below with reference to FIGS. 16 to 24 to be sectional views showing a manufacturing process in order.
At a step shown in FIG. 16, first of all, a silicon carbide substrate 301 containing an n-type impurity in a relatively high concentration (n+) is prepared and silicon carbide is grown on one of main surfaces by an epitaxial growth method to form an n-type epitaxial layer 303 having an impurity concentration of 8xc3x971014 cmxe2x88x923 (FIG. 17). The n-type epitaxial layer 303 has a thickness of approximately 50 xcexcm.
At a step shown in FIG. 18, next, a p-type impurity ion is implanted into a main surface of the n-type epitaxial layer 303 to form a p-type impurity layer 302 containing a p-type impurity in a relatively high concentration (p+) by thermal diffusion.
At a step shown in FIG. 19, then, the p-type impurity layer 302 provided on the outer periphery of the operation region is removed by using a photolithographic technique and an anisotropic etching technique such that the p-type impurity layer 302 remains only in a portion to be the operation region. At this time, a part of the n-type epitaxial layer 303 is removed together such that a step shape having a protrusion PP and a base bottom portion BP is formed.
The protrusion PP has a bevel structure in which a side surface thereof is formed with an inclination and a side surface of the n-type epitaxial layer 303 has an inclination with respect to a pn junction interface of the n-type epitaxial layer 303 and the p-type impurity layer 302 remaining in the operation region.
At a step shown in FIG. 20, next, a resist mask RM1 is formed over the whole surface and an opening OP3 is provided to surround the protrusion PP in the resist mask RM1 provided on the base bottom portion BP as shown in FIG. 21. A p-type impurity is implanted into a main surface of the n-type epitaxial layer 303 through the opening OP3 by ion implantation, thereby forming a p-type impurity layer 308 containing the p-type impurity in a relatively low concentration (pxe2x88x92).
After the resist mask RM1 is removed, a silicon oxide film 307 is formed over the whole surface at a step shown in FIG. 22.
At a step shown in FIG. 23, then, the silicon oxide film 307 is removed such that an upper part of the p-type impurity layer 302 to be the operation region acts as an opening OP4. At this time, the silicon oxide film 307 is selectively removed such that the side surface of the protrusion PP and the base bottom portion BP are reliably covered with the silicon oxide film 307.
At a step shown in FIG. 24, thereafter, an anode electrode 304 is formed on the p-type impurity layer 302 exposed by the opening OP4. Finally, a cathode electrode 305 is formed on the other main surface of the silicon carbide substrate 301. Consequently, the silicon carbide diode 90 shown in FIG. 15 is obtained.
Although the p-type impurity layer 308 constitutes the field limiting ring, the silicon carbide has a breakdown electric field which is approximately ten times as great as that of silicon. Based on a simple calculation, therefore, it is sufficient that the number of the field limiting rings is one-tenth of that in the case in which the field limiting ring is provided in a silicon device.
While the SIPOS structure or the field limiting ring structure has been employed for the junction termination processing structure in the conventional semiconductor device as described above, there have been the following problems.
More specifically, the conductivity of the SIPOS film has a great temperature dependency and is increased when a temperature is raised. The conductivity is varied by approximately two digits at a room temperature and a temperature of 125xc2x0 C. Therefore, a voltage blocking capability is varied at the room temperature and the temperature of 125xc2x0 C. and a leakage current is increased at the temperature of 125xc2x0 C. Consequently, the temperature is further raised and a leakage current is further increased with a current loss generated by a current leakage at a high temperature. By the positive feedback function, there has been a possibility that the operation of the semiconductor device might be uncontrollable.
Moreover, the conductivity of the SIPOS film is determined by a concentration of contained oxygen. However, it is not easy to control the oxygen concentration with high precision in the manufacturing process.
On the other hand, the impurity concentration and the diffusion depth of the field limiting ring are usually different from those of the main junction in the operation region. The field limiting ring is provided separately from a step of forming the main junction such that an optimum state is brought. However, the manufacturing process becomes complicated and a reduction in a manufacturing cost cannot be attained.
It is an object of the present invention to provide a semiconductor device in which an operation thereof can be prevented from being uncontrollable to obtain a high reliability, manufacture can be carried out easily and a manufacturing cost can be reduced.
The present invention is directed to a semiconductor device including an underlying semiconductor layer having a region in which a pn junction is to be formed, a junction end of the pn junction reaching a main surface of the underlying semiconductor layer, and at least one Schottky metal layer provided like a ring on the main surface of the underlying semiconductor layer in Schottky contact with the underlying semiconductor layer to surround the region.
The Schottky metal layer is provided like a ring on the main surface of the underlying semiconductor layer in Schottky contact with the underlying semiconductor layer to surround a region in which the pn junction is formed. Therefore, a depleted region having a very low impurity concentration is formed in the main surface of the underlying semiconductor layer to have such a depth as to be almost equal to or greater than a depth of the main junction corresponding to a portion in which the Schottky metal layer is formed. When a backward bias is applied to the semiconductor device, a depletion layer is first formed around the main junction. As the backward bias is increased, the depletion layer is extended toward the outer peripheral side and the main junction and the depleted region punch through before avalanche breakdown of the main junction is caused. Consequently, the depletion layer is expanded to have such a depth as to be almost equal to or greater than the depth of the main junction and is extended toward the outer peripheral side, and a maximum electric field of a curved portion of the main junction can be suppressed and a high breakdown voltage can be obtained. Differently from the case in which a field limiting ring is used as a junction termination processing structure, moreover, it is not necessary to form a dedicated pn junction in the surface of the semiconductor substrate. Consequently, a manufacturing method can be simplified and a manufacturing cost can be reduced. Differently from the case in which an SIPOS film is used for the junction termination processing structure, furthermore, a component having a great temperature dependency is not used. Therefore, even if a rise in a temperature is generated, an operation can be prevented from being uncontrollable. Thus, a semiconductor device having a high reliability can be obtained.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.